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Process optimization for sub-100-nm gate patterns using phase edge lithography

dc.contributor.authorvan Ingen Schenau, K.
dc.contributor.authorVleeming, Bert
dc.contributor.authorGehoel-van Ansem, W. F.
dc.contributor.authorWong, P.
dc.contributor.authorVandenberghe, Geert
dc.date.accessioned2021-10-14T18:04:47Z
dc.date.available2021-10-14T18:04:47Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5737
dc.sourceIIOimport
dc.titleProcess optimization for sub-100-nm gate patterns using phase edge lithography
dc.typeProceedings paper
dc.contributor.imecauthorVandenberghe, Geert
dc.source.peerreviewno
dc.source.beginpage200
dc.source.endpage211
dc.source.conferenceAdvances in Resist Technology and Processing XVIII
dc.source.conferencedate26/02/2001
dc.source.conferencelocationSanta Clara, CA USA
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 4345


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