Process optimization for sub-100-nm gate patterns using phase edge lithography

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Authors
van Ingen Schenau, K.; Vleeming, Bert; Gehoel-van Ansem, W. F.; Wong, P.; Vandenberghe, Geert
Conference
Advances in Resist Technology and Processing XVIII
Title
Process optimization for sub-100-nm gate patterns using phase edge lithography
Publication type
Proceedings paper
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