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Conference contributions
Process optimization for sub-100-nm gate patterns using phase edge lithography
Publication:
Process optimization for sub-100-nm gate patterns using phase edge lithography
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Date
2001
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
van Ingen Schenau, K.
;
Vleeming, Bert
;
Gehoel-van Ansem, W. F.
;
Wong, P.
;
Vandenberghe, Geert
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1961
since deposited on 2021-10-14
Acq. date: 2025-12-10
Citations
Metrics
Views
1961
since deposited on 2021-10-14
Acq. date: 2025-12-10
Citations