Effect of Traps in Si/SiGe NPN Selectors for Cross-Point Memory Array Architecture

Abstract

A latch-up bipolar junction transistor (BJT) selector device for memory crossbar architecture was fabricated using p+–Si 1−x Gex as floating base sandwiched between n+-Si layers. The Ge concentration in the SiGe layers has varied between 25% and 40% and the base thickness between 25 and 35nm. The stack was etched with diameter of the device varied from 50 to 150nm. Finally, the devices were encapsulated using different materials. By using end of line (EOL) high-pressure (HP) H2 annealing, the latch-up voltage ( Von) reduced from 2.75 to 2.2 V (for 150-nm device diameter) and the nonlinearity (NL = ratio of currents at Von+100 mV and that at the half of operating voltage) improved from 104 to 3×104 . This behavior was also studied by 1-D technology computer aided design (TCAD) simulation by introducing traps in the device. Traps at the floating base cause loss of hole, resulting in increased latch-up voltage and elevated leakage current. AlOx and SiNx offer superior passivation to deposited SiO2, enhancing device performance. The device demonstrates excellent performance, achieving a low Von of 2.2 V, exceptional endurance exceeding 1010 cycles (under 0–3 V stress for 100 ns), and a high on-state current density of 14MA/cm2 at 3 V. The results demonstrate the viability of the fabricated n-type/p-type/n-type (NPN) device as a high-endurance selector for crossbar memory architectures.