SOT-MRAM Bitcell Scaling With BEOL Read Selectors: A DTCO Study

Abstract

This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive design-technology co-optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10%–40%) bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1–100) s retention targets. This is particularly to attribute to their: 1) more available Si fins for write transistor (WRT) and 2) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3–5) ns and the imperfectly rectifying diode selectors suffering (2.5–5) × energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs toward holistic power-performance-area (PPA) scaling of SOT-MRAM.