Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications

Abstract

Advancements in 2.5D and 3D technology have emerged as breakthroughs within the realm of semiconductor innovation with enhanced performance, efficiency and miniaturization of semiconductor devices. Given the substantial space occupied by SRAM in modern day system-on-chips (SoCs), 3D SRAM promises footprint reduction and enhanced chip performance. Face-to-face (F2F) hybrid bonding is extensively used to bond two or more operational silicon chips to get 3D stacked chips. However, these bond pads have significantly higher pitch when compared with the SRAM bit-cell dimensions and hence the data bandwidth is limited by the bond pitch of the linearly arranged hybrid bond pads. This work demonstrates a staggered pillar configuration to overcome the 3D F2F bond pad pitch limit and hence increasing the bandwidth of the 3D SRAM macro significantly. The 3D SRAM macro with staggered pillar configuration achieves 2x, 4x and 7x improvement in the bandwidth for 400 nm, 700 nm and 1 µm bond pad pitches, respectively, compared to non-staggered 3D configuration in A14 nanosheet technology.