Direct extraction of contact and S/D epi access resistance components on 45nm Gate Pitch NS-based n-FET devices for the 2nm node

Abstract

We report on a new methodology to perform direct extraction of contact and source/drain epi resistance components in NS-based n-FET device (n-NSFET) with 45nm Gate Pitch and 16nm Gate Length. We have combined this method with advanced metrology (XTEM and scalpel SSRM) to analyze the device topology and carrier distribution, and to extract contact resistivity. We have investigated the impact of post S/D epi spike anneal and compared the results with reference contact resistivity values extracted on TLM test-structures. We have used this information to calibrate a TCAD deck and propose solutions to boost device performance.