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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

dc.contributor.authorBadaroglu, Mustafa
dc.contributor.authorTiri, Kris
dc.contributor.authorDonnay, Stephane
dc.contributor.authorWambacq, Piet
dc.contributor.authorVerbauwhede, Ingrid
dc.contributor.authorGielen, Georges
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-10-14T21:07:39Z
dc.date.available2021-10-14T21:07:39Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5976
dc.sourceIIOimport
dc.titleClock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
dc.typeProceedings paper
dc.contributor.imecauthorBadaroglu, Mustafa
dc.contributor.imecauthorDonnay, Stephane
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorGielen, Georges
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecDonnay, Stephane::0000-0003-2489-4793
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.source.peerreviewno
dc.source.beginpage399
dc.source.endpage404
dc.source.conferenceProceedings 39th Design Automation Conference
dc.source.conferencedate10/06/2002
dc.source.conferencelocationNew Orleans, LA USA
imec.availabilityPublished - imec


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