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Conference contributions
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
Publication:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
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Date
2002
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Badaroglu, Mustafa
;
Tiri, Kris
;
Donnay, Stephane
;
Wambacq, Piet
;
Verbauwhede, Ingrid
;
Gielen, Georges
;
De Man, Hugo
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1928
since deposited on 2021-10-14
Acq. date: 2025-12-10
Citations
Metrics
Views
1928
since deposited on 2021-10-14
Acq. date: 2025-12-10
Citations