Multi-node scaling potential of monolithic CFET

Abstract

This paper explores design strategies and Power-Performance-Area (PPA) trade-offs for scaling monolithic Complementary FETs (CFETs) from the A7 to A3 technology nodes. At A7 node, we demonstrate gate and Middle-of-Line (MOL) parasitic capacitance optimization to match N2 node performance. At A5 node, an Omega-gate Forksheet (O-FS) architecture keeps performance at the same level at lower sheet width. At A3 node, asymmetric crystal orientation engineering enhances drive current and supports aggressive area scaling targets.