Nanosheet field-effect transistors (NS FETs) utilizing the gate-all-around (GAA) architecture have emerged as the primary alternative to tri-gate FinFETs. However, several technical issues arise in the fabrication of NS FETs, with interface trap states being a critical concern. These traps primarily originate from defects at the Si/SiO2 interface during O3 treatment prior to interlayer formation. As NS FETs transition toward higher numbers of vertically stacked nanosheets to enhance performance, the impact of these interface traps becomes increasingly significant. In this study, we investigate the influence of two distinct types of interface traps—donor-like and acceptor-like—on the DC characteristics of NS FETs. We systematically evaluate the sensitivity of electrical parameters to trap configurations and provide a guideline for optimizing cutting-edge nanosheet device technologies.
