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In-line electrical metrology for high-k gate dielectrics deposited by atomic layer CVD

dc.contributor.authorDe Witte, Hilde
dc.contributor.authorPassefort, Sophie
dc.contributor.authorBesling, Wim
dc.contributor.authorMaes, Jos
dc.contributor.authorEason, K.
dc.contributor.authorYoung, Edward
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-10-14T21:25:38Z
dc.date.available2021-10-14T21:25:38Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6228
dc.sourceIIOimport
dc.titleIn-line electrical metrology for high-k gate dielectrics deposited by atomic layer CVD
dc.typeMeeting abstract
dc.contributor.imecauthorHeyns, Marc
dc.source.peerreviewno
dc.source.beginpage719
dc.source.conference201st Meeting of the Electrochemical Society. Rapid Thermal and Other Short Time Processing Technologies III
dc.source.conferencedate12/05/2002
dc.source.conferencelocationPhiladelphia, PA USA
imec.availabilityPublished - imec
imec.internalnotesMeeting Abstracts; Vol. 2002-1


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