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Shrinking from 0.25 μm down to 0.12 μm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs

dc.contributor.authorDieudonné, F.
dc.contributor.authorHaendler, S.
dc.contributor.authorJomaah, J.
dc.contributor.authorRaynaud, C.
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorvan Meer, Hans
dc.contributor.authorBalestra, F.
dc.date.accessioned2021-10-14T21:32:10Z
dc.date.available2021-10-14T21:32:10Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6283
dc.sourceIIOimport
dc.titleShrinking from 0.25 μm down to 0.12 μm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs
dc.typeProceedings paper
dc.contributor.imecauthorDe Meyer, Kristin
dc.source.peerreviewno
dc.source.beginpage33
dc.source.endpage36
dc.source.conferenceProceedings Ultimate Integration of Silicon (ULIS) Workshop
dc.source.conferencedate7/03/2002
dc.source.conferencelocationMünchen Germany
imec.availabilityPublished - imec


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