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Investigation of poly-Si/HfO2 gate stacks in a self-aligned 65 nm NMOS process flow

dc.contributor.authorKubicek, Stefan
dc.contributor.authorCarter, Richard
dc.contributor.authorCartier, Eduard
dc.contributor.authorLujan, Guilherme
dc.contributor.authorKerber, Andreas
dc.contributor.authorKaushik, Vidya
dc.contributor.authorChen, P.J.
dc.contributor.authorDe Gendt, Stefan
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-10-14T22:05:20Z
dc.date.available2021-10-14T22:05:20Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6498
dc.sourceIIOimport
dc.titleInvestigation of poly-Si/HfO2 gate stacks in a self-aligned 65 nm NMOS process flow
dc.typeOral presentation
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDe Gendt, Stefan
dc.contributor.imecauthorHeyns, Marc
dc.contributor.orcidimecDe Gendt, Stefan::0000-0003-3775-3578
dc.source.peerreviewno
dc.source.conference33rd IEEE Semiconductor Interface Specialists Conference - SISC
dc.source.conferencedate5/12/2002
dc.source.conferencelocationSan Diego, CA USA
imec.availabilityPublished - imec


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