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dc.contributor.authorPalacin, J.
dc.contributor.authorSalleras, M.
dc.contributor.authorMarco., S.
dc.contributor.authorMarty, A.
dc.contributor.authorTasselli, J.
dc.contributor.authorVan Hoof, Rita
dc.contributor.authorBeyne, Eric
dc.contributor.authorVendier, O.
dc.contributor.authorCoella-Vera, A.
dc.date.accessioned2021-10-14T22:40:28Z
dc.date.available2021-10-14T22:40:28Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6685
dc.sourceIIOimport
dc.titleDynamic compact thermal models for an ultra thin chip stacking technology
dc.typeProceedings paper
dc.contributor.imecauthorVan Hoof, Rita
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage93
dc.source.endpage100
dc.source.conferenceProceedings of the 3rd Eurosime Conference
dc.source.conferencedate14/04/2002
dc.source.conferencelocationParis France
imec.availabilityPublished - open access


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