Show simple item record

70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme

dc.contributor.authorvan Meer, Hans
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-14T23:37:50Z
dc.date.available2021-10-14T23:37:50Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6952
dc.sourceIIOimport
dc.title70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme
dc.typeProceedings paper
dc.contributor.imecauthorDe Meyer, Kristin
dc.source.peerreviewno
dc.source.beginpage170
dc.source.endpage171
dc.source.conferenceSymposium on VLSI Technology: Digest of Technical Papers
dc.source.conferencedate11/06/2002
dc.source.conferencelocationHonolulu, HI USA
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record