70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme
dc.contributor.author | van Meer, Hans | |
dc.contributor.author | De Meyer, Kristin | |
dc.date.accessioned | 2021-10-14T23:37:50Z | |
dc.date.available | 2021-10-14T23:37:50Z | |
dc.date.issued | 2002 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/6952 | |
dc.source | IIOimport | |
dc.title | 70 nm fully-depleted SOI cmos using a new fabrication scheme: the spacer/replacer scheme | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | De Meyer, Kristin | |
dc.source.peerreview | no | |
dc.source.beginpage | 170 | |
dc.source.endpage | 171 | |
dc.source.conference | Symposium on VLSI Technology: Digest of Technical Papers | |
dc.source.conferencedate | 11/06/2002 | |
dc.source.conferencelocation | Honolulu, HI USA | |
imec.availability | Published - imec |
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