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A unified hot carrier degradation model for integrated lateral and vertical nDMOS transistors

dc.contributor.authorMoens, P.
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorBolognesi, D.
dc.date.accessioned2021-10-15T05:45:57Z
dc.date.available2021-10-15T05:45:57Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7908
dc.sourceIIOimport
dc.titleA unified hot carrier degradation model for integrated lateral and vertical nDMOS transistors
dc.typeProceedings paper
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.source.peerreviewno
dc.source.beginpage88
dc.source.endpage91
dc.source.conference15th International Symposium on Power Semiconductor Devices & ICs - ISPSD
dc.source.conferencedate14/04/2003
dc.source.conferencelocationCambridge UK
imec.availabilityPublished - imec


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