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Bias stress in pentacene transistors measured by four probe transistor structures

dc.contributor.authorGenoe, Jan
dc.contributor.authorSteudel, Soeren
dc.contributor.authorDe Vusser, Stijn
dc.contributor.authorVerlaak, Stijn
dc.contributor.authorJanssen, Dimitri
dc.contributor.authorHeremans, Paul
dc.date.accessioned2021-10-15T13:32:45Z
dc.date.available2021-10-15T13:32:45Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8948
dc.sourceIIOimport
dc.titleBias stress in pentacene transistors measured by four probe transistor structures
dc.typeProceedings paper
dc.contributor.imecauthorGenoe, Jan
dc.contributor.imecauthorHeremans, Paul
dc.contributor.orcidimecGenoe, Jan::0000-0002-4019-5979
dc.contributor.orcidimecHeremans, Paul::0000-0003-2151-1718
dc.source.peerreviewno
dc.source.beginpage413
dc.source.endpage416
dc.source.conferenceProceedings of the 34th European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate21/09/2004
dc.source.conferencelocationLeuven Belgium
imec.availabilityPublished - imec


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