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Impact of STI width and spacing on the stress generation in deep submicron CMOS

dc.contributor.authorPoyai, A.
dc.contributor.authorRittaporn, I.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.contributor.authorRooyackers, Rita
dc.date.accessioned2021-10-15T15:36:03Z
dc.date.available2021-10-15T15:36:03Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9461
dc.sourceIIOimport
dc.titleImpact of STI width and spacing on the stress generation in deep submicron CMOS
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage307
dc.source.endpage316
dc.source.conferenceHigh Purity Silicon VIII
dc.source.conferencedate3/10/2004
dc.source.conferencelocationHonolulu, HI USA
imec.availabilityPublished - open access
imec.internalnotesElectrochemical Society Proceedings; Vol. PV 2004-05


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