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A finite element study of process induced stress in the transistor channel: effects of silicide contact and gate stack

dc.contributor.authorTorregiani, Cristina
dc.contributor.authorLiu, Joy
dc.contributor.authorVandevelde, Bart
dc.contributor.authorDegryse, Dominiek
dc.contributor.authorVan Dal, Mark
dc.contributor.authorBenedetti, Alessandro
dc.contributor.authorLauwers, Anne
dc.contributor.authorMaex, Karen
dc.date.accessioned2021-10-15T16:42:09Z
dc.date.available2021-10-15T16:42:09Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9688
dc.sourceIIOimport
dc.titleA finite element study of process induced stress in the transistor channel: effects of silicide contact and gate stack
dc.typeProceedings paper
dc.contributor.imecauthorVandevelde, Bart
dc.contributor.imecauthorVan Dal, Mark
dc.contributor.imecauthorLauwers, Anne
dc.contributor.imecauthorMaex, Karen
dc.contributor.orcidimecVandevelde, Bart::0000-0002-6753-6438
dc.source.peerreviewno
dc.source.beginpage61
dc.source.endpage68
dc.source.conferenceEuroSimE: 5th Int. Conf. on Thermal & Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems
dc.source.conferencedate9/05/2004
dc.source.conferencelocationBrussels Belgium
imec.availabilityPublished - imec


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