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Selection of ferroelectric/high-k gate stack combination for optimized FeFET performance

dc.contributor.authorXu, Zhen
dc.contributor.authorViapiana, Matteo
dc.contributor.authorKaczer, Ben
dc.contributor.authorGoux, Ludovic
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorWouters, Dirk
dc.date.accessioned2021-10-15T18:05:41Z
dc.date.available2021-10-15T18:05:41Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9949
dc.sourceIIOimport
dc.titleSelection of ferroelectric/high-k gate stack combination for optimized FeFET performance
dc.typeOral presentation
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorGoux, Ludovic
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecGoux, Ludovic::0000-0002-1276-2278
dc.source.peerreviewno
dc.source.conferenceMRS Fall Meeting Symposium D: Materials and Processes for Nonvolatile Memories
dc.source.conferencedate29/11/2004
dc.source.conferencelocationBoston, MA USA
imec.availabilityPublished - imec
imec.internalnotesOral presentation only; No publication in the proceedings


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