Browsing by Author "Bauer, F."
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Publication A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
Publication Analog design challenges and trade-offs using emerging materials and devices
Proceedings paper2007-09, Proceedings of the 37th European Solid-State Device Research Conference - ESSDERC, 11/09/2007, p.123-126Publication Layout options for stability tuning of SRAM cells in multi-gate=FET technologies
Proceedings paper2007, Proceedings of the 33rd European Solid-State Circuits Conference - ESSCIRC, 11/09/2007, p.392-395Publication Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
Proceedings paper2008, IEEE International Conference on IC Design and Technology - ICICDT, 2/06/2008, p.59-62