Browsing by Author "Deshpande, Veeresh Vidyadhar"
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Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication Scaling CMOS beyond Si FinFET: an analog/RF perspective
; ; ; ; ; Proceedings paper2018, 48th European Solid-State Device Research Conference - ESSDERC, 3/09/2018, p.158-161Publication Semiconductor technologies for next generation mobile communications
Proceedings paper2018-11, 14th IEEE International Conference on Solid-State and Integrated Circuit Technology - ICSICT, 31/10/2018, p.1-4