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Browsing by Author "Kim, Cheolgyu"

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    Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery

    Spessot, Alessio  
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    Sharan, Neha  
    ;
    Oh, Hyungrock  
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    Ritzenthaler, Romain  
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    Dentoni Litta, Eugenio  
    Proceedings paper
    2018-01, 2018 IEEE International Memory Workshop (IMW), 13/05/2018, p.1-4
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    Gate-stack engineered NBTI improvements in high-voltage logic-for-memory high-k/metal gate devices

    O'Sullivan, Barry  
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    Ritzenthaler, Romain  
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    Rzepa, G
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    Wu, Zhicheng  
    ;
    Dentoni Litta, Eugenio  
    Proceedings paper
    2019, IEEE International Reliability Physics Symposium - IRPS, 31/03/2019, p.1-8
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    Reliability engineering enabling continued logic for memory device scaling

    O'Sullivan, Barry  
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    Ritzenthaler, Romain  
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    Dentoni Litta, Eugenio  
    ;
    Simoen, Eddy  
    Proceedings paper
    2019, 2019 IEEE International Integrated Reliability Workshop (IIRW), 13/10/2019

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