Browsing by Author "Kim, Myungsun"
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Publication 3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Proceedings paper2019, IEEE International Electron Devices Meeting - IEDM 2019, 7/12/2019, p.238-241Publication Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization
Proceedings paper2018, IEEE International Electron Devices Meeting - IEDM, 2/12/2018, p.508-511Publication Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Proceedings paper2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.828-831