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Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Publication:
Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration
Date
2017
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Mertens, Hans
;
Ritzenthaler, Romain
;
Pena, Vanessa
;
Santoro, Gaetano
;
Kenis, Karine
;
Schulze, Andreas
;
Dentoni Litta, Eugenio
;
Chew, Soon Aik
;
Devriendt, Katia
;
Chiarella, Thomas
;
Demuynck, Steven
;
Yakimets, Dmitry
;
Jang, Doyoung
;
Spessot, Alessio
;
Eneman, Geert
;
Dangol, Anish
;
Lagrain, Pieter
;
Bender, Hugo
;
Sun, Shiyu
;
Korolik, Michael
;
Kioussis, D.
;
Kim, Myungsun
;
Bu, Kyung-Ho
;
Chen, Shih Chung
;
Cogorno, Matt
;
Devrajan, J.
;
Machillot, Jerome
;
Yoshida, Naomi
;
Kim, Namsung
;
Barla, Kathy
;
Mocuta, Dan
;
Horiguchi, Naoto
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2027
since deposited on 2021-10-24
Acq. date: 2025-10-23
Citations
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2027
since deposited on 2021-10-24
Acq. date: 2025-10-23
Citations