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Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration

Date

2017
Proceedings Paper
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dc.contributor.authorMertens, Hans
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorPena, Vanessa
dc.contributor.authorSantoro, Gaetano
dc.contributor.authorKenis, Karine
dc.contributor.authorSchulze, Andreas
dc.contributor.authorDentoni Litta, Eugenio
dc.contributor.authorChew, Soon Aik
dc.contributor.authorDevriendt, Katia
dc.contributor.authorChiarella, Thomas
dc.contributor.authorDemuynck, Steven
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorJang, Doyoung
dc.contributor.authorSpessot, Alessio
dc.contributor.authorEneman, Geert
dc.contributor.authorDangol, Anish
dc.contributor.authorLagrain, Pieter
dc.contributor.authorBender, Hugo
dc.contributor.authorSun, Shiyu
dc.contributor.authorKorolik, Michael
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorPena, Vanessa
dc.contributor.imecauthorSantoro, Gaetano
dc.contributor.imecauthorKenis, Karine
dc.contributor.imecauthorDentoni Litta, Eugenio
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorChiarella, Thomas
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorJang, Doyoung
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorDangol, Anish
dc.contributor.imecauthorLagrain, Pieter
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorMachillot, Jerome
dc.contributor.imecauthorBarla, Kathy
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecChiarella, Thomas::0000-0002-6155-9030
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecLagrain, Pieter::0000-0003-3734-7203
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-24T09:12:54Z
dc.date.available2021-10-24T09:12:54Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/28971
dc.identifier.urlhttp://ieeexplore.ieee.org/document/8268511/
dc.source.beginpage828
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate2/12/2017
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage831
dc.title

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration

dc.typeProceedings paper
dspace.entity.typePublication
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