Browsing by Author "Mattii, Luca"
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Publication CFET standard-cell design down to 3Track height for node 3nm and below
Proceedings paper2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 24/02/2019, p.1096206Publication DTCO exploration for efficient standard cell power rails
Proceedings paper2018, Design-Process-Technology Co-optimization for Manufacturability XII, 25/02/2018, p.105880BPublication EDA role in the design-technology co-optimization towards N7
Proceedings paper2016, CDNLive Cadence User Conference EMEA, 2/05/2016Publication IR-drop aware design and Technology co-optimization for N5 node with different device and cell height options
Proceedings paper2017, IEEE/ACM International Conference on Computer-Aided Design - ICCAD, 18/06/2017, p.89-94Publication Low track height standard cell design in iN7 using scaling boosters
Proceedings paper2017, Design-Process-Technology Co-optimization for Manufacturability XI, 26/02/2017, p.101480YPublication Low track height standard-cells enable high-placement density and low-BEOL cost
Proceedings paper2017, Design-Process-Technology Co-optimization for Manufacturability XI, 26/02/2017, p.1014803Publication Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells
Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.143-144Publication System-level impact of interconnect line-edge roughness
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.67-69Publication Track height reduction for standard-cell in below 5nm node: How low can you go?
Meeting abstract2018, Design-Process-Technology Co-optimization for Manufacturability XII, 25/02/2018, p.1058809Publication Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
Journal article2018, IEEE Transactions on Nanotechnology, (17) 6, p.1259-1269