Browsing by Author "Mukherjee, Subhasish"
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Publication Automated design-for-test for 2.5D and 3D SICs
Journal article2011-09, Chip Scale Review, (?) 5, p.18-22Publication Automation of 3D-DfT insertion
Proceedings paper2011-11, IEEE Asian Test Symposium - ATS, 21/11/2011Publication Automation of 3D-DfT insertion
Proceedings paper2011-09, IEEE International Workshop on Testing Three-Dimensional Stacked ICs- 3D-TEST, 22/09/2011Publication Automation of DfT for 3-D stacked die
Proceedings paper2011, 3-D Architectures for Semiconductor Integration and Packaging, 3-D ASIP, 12/12/2011Publication DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
Publication DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks
Publication Implementation aspects of a 3D DfT architecture
Oral presentation2011, CDNLive! EMEA (Cadence Design Systems)