Browsing by Author "Pan, Chenyun"

Accurate determination of interlayer resistivity of 2-D layered systems: graphene case study

Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

Technology/circuit co-optimization and benchmarking for graphene interconnects at sub-10nm technology node

Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus