Browsing by Author "Papanikolaou, Antonis"
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Publication 3-D technology assessment: path-finding the technology/design sweet-spot
Journal article2009, Proceedings of the IEEE, (97) 1, p.96-107Publication A designer's perspective on future memory architectures for software defined radios
Publication A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
Proceedings paper2004, Proceedings Asia and South Pacific Design Automation Conference - ASP-DAC, 27/01/2004, p.759-761Publication A method and tool for early design/technology search-space exploration for 3D ICs
Publication A system architecture case study for efficient calibration of memory organizations under process variability
Publication A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications
Proceedings paper2005-09, Proceedings International Conference on HW/SW Codesign and System Synthesis, 18/09/2005, p.117-122Publication A tool flow for predicting system level timing failures due to interconnect reliability degradation
Proceedings paper2008, Proceedings 18th ACM Great Lakes Symposiun on VLSI, 4/05/2008, p.291-296Publication Architectural and physical design optimizations for efficient intra-tile communication
Proceedings paper2005, Proceedings International Symposium on System-on-Chip, 15/11/2005, p.112-115Publication At tape-out: can yield in terms of parametric specifications be predicted?
Publication Case study on energy efficient communication design
Publication Combining system scenarios and configurable memories to tolerate unpredictability
Publication Configurable module topology to recover power lost due to current mismatch
Proceedings paper2014, European Photovoltaic Solar Energy Conference and Exhibition - EUPVSEC, 22/09/2014, p.194-197Publication Control for power gating of wires
Journal article2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (18) 9, p.1287-1300Publication Control of low-power on-chip synchronous communication
Meeting abstract2007-07, Advanced Computer Architecture and Compilers for Embedded Systems - ACACES, 15/07/2007, p.29-32Publication Enabling efficient system configurations for dynamic wireless applications using system scenarios
Publication Energy costs of transporting switch control bits for a segmented bus
Proceedings paper2005, Annual Workshop on Circuits, Systems and Signal Processing - ProRISC, 17/11/2005, p.359-364Publication Energy/area/delay trade-offs in the physical design of on-chip segmented buses architecture
Journal article2007-08, IEEE Trans. on Very Large Scale Integration (VLSI) Systems, (15) 8, p.941-944Publication Global interconnect trade-off for technology over memory modules to application level: case study
Proceedings paper2003, 5th ACM/IEEE Intl. Wsh. on System Level Interconnect Prediction, 5/04/2003, p.1-5Publication Memory communication network exploration for low-power distributed memory organisations
Proceedings paper2004, Symposium Proceedings Program Acceleration through Application and Architecture-driven Code Transformations - PA3CT, 13/09/2004, p.25-27Publication Memory communication network exploration for low-power distributed memory organisations
Proceedings paper2004-10, IEEE Workshop on Signal Processing Systems - SIPS, 13/10/2004, p.176-181