Browsing by Author "Pochet, Sandrine"
Now showing 1 - 6 of 6
- Results Per Page
- Sort Options
Publication A high performance 0.18µm elevated source/drain technology with improved manufacturability
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference, 13/09/1999, p.636-639Publication Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy
Proceedings paper1999, International Electron Devices Meeting. Technical digest; 5-8 Dec. 1999; Washington, D.C., USA., p.357-360Publication Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity
Journal article2000, IEEE Trans. Electron Devices, (47) 7, p.1484-1491Publication L-shape spacer architecture for low cost, high performance CMOS
Publication Optimisation of active area edge protection in shallow trench isolation
Proceedings paper2001, ULSI Process Integration II; 26 March 2001; Washington, D.C., USA., p.539-546Publication Optimisation of critical parameters in a low cost, high performance deep submicron CMOS technology