Browsing by Author "Saad, Yves"
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Publication Calibrated Modeling of Line-to-Line Dielectric Reliability: LER Specs to Meet Reliability Constraints at Operating Conditions
Meeting abstract2019, 26th Lithography Workshop, 3/11/2019, p.50Publication Impact of litho-patterning variations on the electrical performance and variability of advanced interconnects
Proceedings paper2018, 25th Lithography Workshop, 17/06/2018, p.18Publication Integration scheme and 3D RC extractions of three-level supervia at 16 nm half-pitch
Journal article2018, Microelectronic Engineering, 191, p.20-24Publication LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration
Journal article2017, Microelectronics Reliability, 76-77, p.131-135Publication Modeling EUVL patterning variability for metal layers in 5nm technology node and its effect on electrical resistance
Proceedings paper2017, Extreme Ultraviolet (EUV) Lithograpgy VIII, 26/02/2017, p.101430IPublication Modeling of via resistance for advanced technology nodes
; ; ; Journal article2017, IEEE Transactions on Electron Devices, (64) 5, p.2306-2313Publication Patterning process exploration of metal 1 layer in 7nm node with 3D pattering flow simulations
Proceedings paper2015, Optical Microlithographies XXVIII, 22/02/2015, p.942609