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Browsing by Author "Schwarzenbach, W."

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    3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters

    Vandooren, Anne  
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    Wu, Zhicheng  
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    Parihar, Narendra  
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    Franco, Jacopo  
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    Parvais, Bertrand  
    Proceedings paper
    2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020
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    A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C

    Lu, Zhichao
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    Collaert, Nadine  
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    Aoulaiche, Marc
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    De Wachter, Bart  
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    De Keersgieter, An  
    Proceedings paper
    2010, IEEE International Elecrton Devices Meeting - IEDM, 6/12/2010, p.288-291
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    Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

    Vandooren, Anne  
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    Wu, Zhicheng  
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    Khaled, Ahmad  
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    Franco, Jacopo  
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    Parvais, Bertrand  
    ;
    Li, W.
    Proceedings paper
    2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T56-T57

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