Browsing by Author "Van Houdt, Jan"
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Publication A 180nm secondary electron injection flash device
Proceedings paper2001, IEEE Non-Volatile Semiconductor Memory Workshop, 12/08/2001, p.62-63Publication A 1Mbit HIMOS® flash memory embedded in a 0.35μm CMOS process
Oral presentation2000, 17th IEEE Nonvolatile Semiconductor Memory Workshop; 13-17 February 2000; Monterey, Ca, USA.Publication A 25ns/byte-programmable low-power SSI flash array with a new low-voltage erase scheme for embedded memory applications
Proceedings paper1995, 14th IEEE Nonvolatile Semiconductor Memory Workshop, 13/08/1995, p.2.2Publication A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications
Journal article1994, IEEE Trans. Components, Packaging, and Manufacturing Techn. Part A, (17) 3, p.380-389Publication A CMOS DC voltage doubler with nonoverlapping switching control
Journal article2001, IEICE Trans. Electronics, (E84C) 2, p.274-277Publication A comprehensive understanding of the erase of TANOS memories through charge separation experiments and simulations
Journal article2011, IEEE Transactions on Electron Devices, (58) 9, p.3147-3155Publication A comprehensive variability study of doped HfO2 FeFET for memory applications
Proceedings paper2022, 14th IEEE International Memory Workshop (IMW), MAR 15-18, 2022, p.85-88Publication A consistent model for oxide trap profiling with the trap spectroscopy by charge injection and sensing (TSCIS) technique
; ; ; ; Zahid, MohammedJournal article2010, Solid-State Electronics, (54) 11, p.1384-1391Publication A consistent model for the SANOS programming operation
Proceedings paper2007, 22nd Non-Voltaile Semiconductor Memory Workshop - NVSMW, 27/08/2007, p.96-97Publication A discharge-based multi-pulse technique (DMP) for probing electron trap energy distribution in high-k materials for Flash memory applications
Proceedings paper2009, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.139-142Publication A FeFET with a novel MFMFIS gate stack: towards energy-efficient and ultrafast NVMs for neuromorphic computing
Publication A figure of merit for flash memory multi-leyer tunnel dielectrics
Proceedings paper2001, Proceedings of the International Conference on Simulation of Semiconductor Physics and Processes - SISPAD, 5/09/2001, p.270-273Publication A flash memory technology with quasi-virtual ground array for low-cost embedded applications
Journal article2001, IEEE Journal of Solid-State Circuits, (36) 6, p.969-978Publication A fully planar stacked gate flash technology with T-shaped floating gate for increased cell coupling ratio
; ; ; ; ; Proceedings paper2007, Proceedings 2nd International Conference on Memory Technology and Design - ICMTD, 7/05/2007, p.243-245Publication A low voltage, high performance 0.35 μm embedded flash EEPROM cell technology
Proceedings paper1998, 16th Nonvolatile Semiconductor Memory Workshop, 2/08/1998, p.106-108Publication A low-cost poly-sidewall erase HIMOSTM technology for 130-90nm embedded flash memories
Oral presentation2004, 20th IEEE Non-Volatile Semiconductor Memory Workshop - NVSMWPublication A model for tunneling current in multi-layer tunnel dielectrics
Journal article2003, Solid-State Electronics, (47) 6, p.1045-1053Publication A new 2 isolated-bits/cell Flash memory device with self aligned split gate structure using ONO stacks for charge storage
Proceedings paper2003, 19th IEEE Nonvolatile Semiconductor Memory Workshop - NVSMW, 16/02/2003, p.46-47Publication A new quantitative model to predict SILC-related disturb characteristics in Flash E2PROM devices
Proceedings paper1996, International Electron Devices Meeting - IEDM, 8/12/1996, p.343-346