Browsing by Author "Yang, Xiaolin"
- Results per page
- Sort Options
Publication A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range
Proceedings paper2023, IEEE 49th European Solid-State Circuits Conference (ESSCIRC), SEP 11-14, 2023, p.253-256Publication A 0.00426 mm(2) 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording
Journal article2022, ELECTRONICS, (11) 21, p.3477Publication A 108 dB DR Delta n-ary sumation - n-ary sumation M Front-End With 720 mV(pp) Input Range and >+/- 300 mV Offset Removal for Multi-Parameter Biopotential Recording
; ; Publication A 108dB DR hybrid-CTDT direct-digitalization $D $R- $RM front-end with 720mVpp input range and >300mV offset removal for wearable bio-signal recording
; ; Publication A 77-dB DR 16-Ch 2nd-order $D- $D $R Neural Recording Chip with 0.0077mm2/Ch
Proceedings paper2021, 2021 Symposium on VLSI Circuits, 13/06/2021Publication A Self-Regulated Reference Generator with Picowatt-VR-Embedded Amplifier Achieving 0.0174%/V LS and-88dB PSRR
Proceedings paper2024, 50th IEEE European Solid-State Electronics Research Conference (ESSERC), SEP 09-12, 2024, p.265-268Publication An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition
; ; ; ; ; Journal article2023, IEEE JOURNAL OF SOLID-STATE CIRCUITS, (58) 4, p.949-960Publication Robust Seizure Prediction Based on Multivariate Empirical Mode Decomposition and Maximum Synchronization Modularity
Proceedings paper2020, 46th Annual Conference of the IEEE-Industrial-Electronics-Society (IECON), OCT 19-21, 2020, p.507-512