2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS
Abstract
This paper introduces a novel sub-bandgap reference (sub-BGR) architecture that combines a single-BJT branch with a PTAT-embedded amplifier featuring an nMOS input stage. This sub-BGR design ensures temperature compensation and line regulation via a straightforward feedback loop, thereby eliminating the need for compensation capacitors, startup circuits, or trimming. Fabricated in a 55-nm CMOS technology, our sub-BGR demonstrates a temperature coefficient of 78.3ppm/◦C with a 0.9V supply, and maintains a line regulation of 0.153%/V across a voltage range of 0.9V to 1.2V, as evidence by measurements from ten chips. Additionally, it achieves a power supply rejection (PSR) ratio of -67dB at 10Hz, while supporting the addition of capacitive loads for further PSR enhancement. Notably, it occupies the smallest area (0.0144mm2) compared to similar sub-BGR designs.
