Publication:
A 0.8V, 113nW Single-BJT Sub-BGR Using an nMOS PTAT Amplifier at 0.9V Supply
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-5497-7103 | |
| cris.virtual.orcid | 0000-0003-4200-0001 | |
| cris.virtual.orcid | 0000-0001-7949-6069 | |
| cris.virtual.orcid | 0000-0001-7179-0343 | |
| cris.virtual.orcid | 0000-0001-9900-528X | |
| cris.virtualsource.department | 5e3a1e00-4f39-467e-805b-cfa1d369a368 | |
| cris.virtualsource.department | 061aa94e-9a35-494d-a68e-50b157d00dd3 | |
| cris.virtualsource.department | 4349d0eb-da53-47e6-a71c-438d56f3cd1c | |
| cris.virtualsource.department | e860cb50-1c74-4b71-a43e-28c38c47381d | |
| cris.virtualsource.department | a76786e4-4d8d-43ef-9c97-3605ed22cb05 | |
| cris.virtualsource.orcid | 5e3a1e00-4f39-467e-805b-cfa1d369a368 | |
| cris.virtualsource.orcid | 061aa94e-9a35-494d-a68e-50b157d00dd3 | |
| cris.virtualsource.orcid | 4349d0eb-da53-47e6-a71c-438d56f3cd1c | |
| cris.virtualsource.orcid | e860cb50-1c74-4b71-a43e-28c38c47381d | |
| cris.virtualsource.orcid | a76786e4-4d8d-43ef-9c97-3605ed22cb05 | |
| dc.contributor.author | Aymerich, Joan | |
| dc.contributor.author | Sawigun, Chutham | |
| dc.contributor.author | Kahraman, Burak | |
| dc.contributor.author | Cisneros Fernandez, Jose | |
| dc.contributor.author | Yang, Xiaolin | |
| dc.contributor.author | Mora Lopez, Carolina | |
| dc.date.accessioned | 2026-05-28T08:36:33Z | |
| dc.date.available | 2026-05-28T08:36:33Z | |
| dc.date.createdwos | 2026-02-10 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | This paper introduces a novel sub-bandgap reference (sub-BGR) architecture that combines a single-BJT branch with a PTAT-embedded amplifier featuring an nMOS input stage. This sub-BGR design ensures temperature compensation and line regulation via a straightforward feedback loop, thereby eliminating the need for compensation capacitors, startup circuits, or trimming. Fabricated in a 55-nm CMOS technology, our sub-BGR demonstrates a temperature coefficient of 78.3ppm/◦C with a 0.9V supply, and maintains a line regulation of 0.153%/V across a voltage range of 0.9V to 1.2V, as evidence by measurements from ten chips. Additionally, it achieves a power supply rejection (PSR) ratio of -67dB at 10Hz, while supporting the addition of capacitive loads for further PSR enhancement. Notably, it occupies the smallest area (0.0144mm2) compared to similar sub-BGR designs. | |
| dc.identifier.doi | 10.1109/iscas56072.2025.11043925 | |
| dc.identifier.isbn | 979-8-3503-5684-7 | |
| dc.identifier.issn | 0271-4302 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59455 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Symposium on Circuits and Systems (ISCAS) | |
| dc.source.conferencedate | 2025-05-25 | |
| dc.source.conferencelocation | London | |
| dc.source.journal | 2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | |
| dc.source.numberofpages | 4 | |
| dc.subject.keywords | BANDGAP | |
| dc.title | A 0.8V, 113nW Single-BJT Sub-BGR Using an nMOS PTAT Amplifier at 0.9V Supply | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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