Browsing by author "Van Dievel, Marc"
Now showing items 1-5 of 5
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A high performance 0.18µm elevated source/drain technology with improved manufacturability
Augendre, Emmanuel; Rooyackers, Rita; Vandamme, Ewout; Perello, Carles; Van Dievel, Marc; Pochet, Sandrine; Badenes, Gonçal (1999) -
Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity
Augendre, Emmanuel; Rooyackers, Rita; Caymax, Matty; Vandamme, Ewout; De Keersgieter, An; Perello, Carles; Van Dievel, Marc; Pochet, Sandrine; Badenes, Gonçal (2000) -
Evaluation of TSV and micro-bump probing for wide I/O testing
Smith, Ken; Hanaway, Peter; Jolley, Mike; Gleason, Reed; Strid, Eric; Daenen, Tom; Dupas, Luc; Knuts, Bruno; Marinissen, Erik Jan; Van Dievel, Marc (2011-09) -
The isocurrent test: a promising tool for wafer-level evaluation of the interconnect reliability
Witvrouw, Ann; Van Dooren, Sofie; Wouters, Dirk; Van Dievel, Marc; Maex, Karen (1996) -
Wafer probing on fine-pitch micro-bumps for 2.5D- and 3D-SICs
Marinissen, Erik Jan; Daenen, Tom; Dupas, Luc; Van Dievel, Marc; Hanaway, Peter; Kiesewetter, Joerg; Smith, Ken; Strid, Eric; Thaerigen, Thomas (2011)