Browsing by author "Mirabelli, Gioele"
Now showing items 1-14 of 14
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Analysis of advanced technology nodes and h-NA EUV introduction: a cost perspective
Mirabelli, Gioele; Wang, Jane; Trivkovic, Darko; Weckx, Pieter; Spessot, Alessio; Ronse, Kurt; Kim, Ryan Ryoung han; Hellings, Geert; Ryckaert, Julien (2021) -
Challenges with SOT-MRAM integration towards N5 node and beyond
Gupta, Mohit; Perumkunnil, Manu; Yasin, Farrukh; Mirabelli, Gioele; Garello, K.; Gupta, Anshul; Furnemont, Arnaud; Kar, Gouri Sankar (2022) -
Curvilinear Standard Cell Design for Semiconductor Manufacturing
Kim, Ryan Ryoung han; Hwang, Soobin; Oak, Apoorva; Sherazi, Yasser; Chang, Hsinlan; Yang, Kiho; Mirabelli, Gioele (2024) -
Design enablement of CFET devices for sub-2nm CMOS nodes
Zografos, Odysseas; Chehab, Bilal; Schuddinck, Pieter; Mirabelli, Gioele; Kakarla, Naveen; Xiang, Yang; Weckx, Pieter; Ryckaert, Julien (2022-05-19) -
Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm
Chehab, Bilal; Ryckaert, Julien; Schuddinck, Pieter; Weckx, Pieter; Horiguchi, Naoto; Mirabelli, Gioele; Spessot, Alessio; Na, Myung Hee (2021) -
DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies
Garcia Bardon, Marie; Wuytens, Pieter; Ragnarsson, Lars-Ake; Mirabelli, Gioele; Jang, Doyoung; Willems, Geert; Mallik, Arindam; Spessot, Alessio; Ryckaert, Julien; Parvais, Bertrand (2020) -
From Design to System-Technology optimization for CMOS
Ryckaert, Julien; Chehab, Bilal; Jang, Doyoung; Mirabelli, Gioele; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Zografos, Odysseas; Ahmed, Zubair; Weckx, Pieter; Hellings, Geert (2021) -
High-Density Standard Cell Libraries with Backside Power Options in A14 Nanosheet Node
Kükner, Halil; Mirabelli, Gioele; Yang, Sheng; Zhou, Yun; Makarov, Alexander; Xiang, Yang; Boemmels, Juergen; Veloso, Anabela; Zografos, Odysseas; Weckx, Pieter; Ryckaert, Julien; Hellings, Geert (2024) -
Increasing Functionality of Wafer's Backside: Analysis of Si and WS2 Backside Power-Switch
Mirabelli, Gioele; Chen, Rongmei; Ahmed, Zubair; Chehab, Bilal; Zografos, Odysseas; Hiblot, Gaspard; Weckx, Pieter; Hellings, Geert; Ryckaert, Julien (2023) -
Manufacturing-friendly curvilinear standard cell design
Kim, Ryan Ryoung han; Oak, Apoorva; Sherazi, Yasser; Mirabelli, Gioele; Hwang, Soobin; Yang, Kiho; Chang, Hsinlan (2024) -
Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network
Chen, Rongmei; Lofrano, Melina; Mirabelli, Gioele; Sisto, Giuliano; Yang, Simei; Jourdain, Anne; Schleicher, Filip; Veloso, Anabela; Zografos, Odysseas; Weckx, Pieter; Hiblot, Gaspard; Van der Plas, Geert; Hellings, Geert; Ryckaert, Julien; Beyne, Eric (2022) -
Power, Performance, Area, and Cost Analysis of Face-to-Face-Bonded 3-D ICs
Agnesina, Anthony; Brunion, Moritz; Kim, Jinwoo; Garcia-Ortiz, Alberto; Milojevic, Dragomir; Catthoor, Francky; Mirabelli, Gioele; Komalan, Manu; Lim, Sung Kyu (2023) -
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
Roda Neve, César; Schuddinck, Pieter; Bufler, Fabian; Xiang, Yang; Farokhnejad, Anita; Mirabelli, Gioele; Vandooren, Anne; Chehab, Bilal; Gupta, Anshul; Hellings, Geert; Ryckaert, Julien (2022-06) -
The Environmental Impact of CMOS Logic Technologies
Ragnarsson, Lars-Ake; Garcia Bardon, Marie; Wuytens, Pieter; Mirabelli, Gioele; Jang, Doyoung; Willems, Geert; Mallik, Arindam; Spessot, Alessio; Ryckaert, Julien; Parvais, Bertrand (2022)