Browsing by author "Goel, Sandeep K."

3D design-for-test architecture

Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03)

Automated design-for-test for 2.5D and 3D SICs

Marinissen, Erik Jan; Konijnenburg, Mario; Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Goel, Sandeep K. (2011-09)

Automation of 3D DfT insertion and interconnect test generation

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011)

Automation of 3D-DfT insertion

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-11)

Automation of 3D-DfT insertion

Deutsch, Sergej; Chickermane, Vivek; Keller, Brion; Mukherjee, Subhasish; Konijnenburg, Mario; Marinissen, Erik Jan; Goel, Sandeep K. (2011-09)

DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks

Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Sood, Navdeep; Goel, Sandeep K.; Chen, Ji-Jan; Mehta, Ashok; Lee, Frank; Marinissen, Erik Jan (2012-11)

DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM

Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K.; Marinissen, Erik Jan (2012-05)

IEEE Std P1838: 3D test access standard under development

Cron, Adam; Marinissen, Erik Jan; Goel, Sandeep K.; McLaurin, Teresa; Bhatia, Sandeep (2019-03)

Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base

Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep K.; Wu, Cheng-Wen (2011-11)

Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study

Goel, Sandeep K.; Adham, Saman; Wang, Min-Jer; Lee, Frank; Chickermane, Vivek; Keller, Brion; Valind, Thomas; Marinissen, Erik Jan (2019-03)

Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs

Noia, Brandon; Chakrabarty, Krishnendu; Goel, Sandeep K.; Marinissen, Erik Jan; Verbree, Jouke (2011-11)

Testing of SOCs with hierarchical cores: common fallacies, test-access optimization, and test scheduling

Goel, Sandeep K.; Marinissen, Erik Jan; Sehgal, Anuja; Chakrabarty, Krishnendu (2009)