Browsing by author "Chi, Chun-Chuan"
Now showing items 1-10 of 10
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3D design-for-test architecture
Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion; Chickermane, Vivek; Goel, Sandeep K. (2019-03) -
3D DfT architecture for pre-bond and post-bond testing
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11) -
A DfT architecture for 3D-SICs based on a standardizable die wrapper
Marinissen, Erik Jan; Chi, Chun-Chuan; Konijnenburg, Mario; Verbree, Jouke (2012-02) -
A standardizable 3D DfT architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010) -
An IEEE Std 1500-based 3D design-for-test architecture
Marinissen, Erik Jan; Chi, Chun-Chuan; Verbree, Jouke; Konijnenburg, Mario (2010-11) -
DfT architecture for 3D-SICs with multiple towers
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011-05) -
DfT architecture for multi-tower 3D-SICs
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011) -
Low-cost post-bond testing of 3D-ICs containing a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2014-11) -
Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep K.; Wu, Cheng-Wen (2011-11) -
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base
Chi, Chun-Chuan; Marinissen, Erik Jan; Goel, Sandeep Kumar; Wu, Cheng-Wen (2011-09)