Browsing by author "Choi, M."
Now showing items 1-5 of 5
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Analysis of microbump induced stress effects in 3D stacked IC technologies
Ivankovic, Andrej; Van der Plas, Geert; Moroz, V.; Choi, M.; Cherman, Vladimir; Mercha, Abdelkarim; Marchal, Pol; Gonzalez, Mario; Eneman, Geert; Zhang, Wenqi; Buisson, Thibault; Detalle, Mikael; La Manna, Antonio; Verkest, Diederik; Beyer, Gerald; Beyne, Eric; Vandevelde, Bart; De Wolf, Ingrid; Vandepitte, Dirk (2012) -
Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
Mercha, Abdelkarim; Van der Plas, Geert; Moroz, V.; De Wolf, Ingrid; Asimakopoulos, Panagiotis; Minas, Nikolaos; Domae, Shinichi; Perry, Dan; Choi, M.; Redolfi, Augusto; Okoro, Chukwudi; Yang, Yu; Van Olmen, Jan; Thangaraju, Sarasvathi; Sabuncuoglu Tezcan, Deniz; Soussan, Philippe; Cho, Jong Hoon; Yakovlev, A.; Marchal, Pol; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2010) -
Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
Guo, Wei; Moroz, Victor; Van der Plas, Geert; Choi, M.; Redolfi, Augusto; Smith, L.; Eneman, Geert; Van Huylenbroeck, Stefaan; Su, P.D.; Ivankovic, Andrej; De Wachter, Bart; Debusschere, Ingrid; Croes, Kris; De Wolf, Ingrid; Mercha, Abdelkarim; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2013) -
Noise coupling between TSVs and active devices: planar nMOSFETs vs. nFinFETs
Sun, Xiao; Rouhi Najaf Abadi, Alireza; Guo, Wei; Bel Ali, K.; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; De Wolf, Ingrid; Raskin, J.P.; Van der Plas, Geert; Beyne, Eric; Absil, Philippe (2015) -
Through silicon via to FinFET noise coupling in 3-D integrated circuits
Rouhi Najaf Abadi, Alireza; Guo, Wei; Sun, Xiao; Ben Ali, K.; Raskin, J.P; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; Van der Plas, Geert; De Wolf, Ingrid; Beyne, Eric; Absil, Philippe (2015)