Browsing by author "Soussou, Assawer"
Now showing items 1-4 of 4
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Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
Soussou, Assawer; Schram, Tom; Miyaguchi, Kenichi; Chakarov, Ivan; Parvais, Bertrand; Ervin, Joseph (2020) -
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Ahmed, Zubair; Afzalian, Aryan; Schram, Tom; Jang, Doyoung; Verreck, Devin; Smets, Quentin; Schuddinck, Pieter; Chehab, Bilal; Sutar, Surajit; Arutchelvan, Goutham; Soussou, Assawer; Asselberghs, Inge; Spessot, Alessio; Radu, Iuliana; Parvais, Bertrand; Ryckaert, Julien; Na, Myung Hee (2020) -
Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Baudot, Sylvain; Soussou, Assawer; Milenin, Alexey; Ervin, Joe; Demuynck, Steven (2018) -
Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Baudot, Sylvain; Soussou, Assawer; Milenin, Alexey; Hopf, Toby; Wang, Shouhua; Weckx, Pieter; Vincent, Benjamin; Ervin, Joe; Demuynck, Steven (2019)