Browsing by author "Patli, Sudhir"
Now showing items 1-3 of 3
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Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond
Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021) -
Enabling sub-5nm CMOS technology scaling thinner and taller!
Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019) -
Interconnect Design-Technology Co-Optimization for Sub-3nm Technology Nodes
Baert, Rogier; Ciofi, Ivan; Patli, Sudhir; Zografos, Odysseas; Sarkar, Satadru; Chehab, Bilal; Jang, Doyoung; Spessot, Alessio; Ryckaert, Julien; Tokei, Zsolt (2020)