Browsing by author "Chava, Bharani"
Now showing items 1-13 of 13
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Architectural strategies in standard-cell design for the 7 nm and beyond technology node
Sherazi, Yasser; Chava, Bharani; Debacker, Peter; Garcia Bardon, Marie; Schuddinck, Pieter; Firouzi, Farshad; Raghavan, Praveen; Mercha, Abdelkarim; Verkest, Diederik; Ryckaert, Julien (2016) -
Backside power delivery as a scaling knob for future systems
Chava, Bharani; Shaik, Khaja Ahmad; Jourdain, Anne; Guissi, Sofiane; Weckx, Pieter; Ryckaert, Julien; Van der Plas, Geert; Spessot, Alessio; Beyne, Eric; Mocuta, Anda (2019) -
Design technology co-optimization for a robust 10nm solution for logic design and Sram
Vandewalle, Boris; Chava, Bharani; Sakhare, Sushil; Ryckaert, Julien; Dusa, Mircea (2014) -
Design technology co-optimization for N10
Ryckaert, Julien; Raghavan, Praveen; Baert, Rogier; Garcia Bardon, Marie; Dusa, Mircea; Mallik, Arindam; Sakhare, Sushil; Vandewalle, Boris; Wambacq, Piet; Chava, Bharani; Croes, Kris; Dehan, Morin; Jang, Doyoung; Leray, Philippe; Liu, Tsung-Te; Miyaguchi, Kenichi; Parvais, Bertrand; Schuddinck, Pieter; Weemaes, Philippe; Mercha, Abdelkarim; Boemmels, Juergen; Horiguchi, Naoto; McIntyre, Greg; Thean, Aaron; Tokei, Zsolt; Cheng, Shaunee; Verkest, Diederik; Steegen, An (2014) -
DTCO exploration for efficient standard cell power rails
Chava, Bharani; Ryckaert, Julien; Mattii, Luca; Sherazi, Yasser; Debacker, Peter; Spessot, Alessio; Verkest, Diederik (2018) -
Extending the roadmap beyond 3nm through system scaling boosters: A case study on buried power rail and backside power delivery
Ryckaert, Julien; Gupta, Anshul; Jourdain, Anne; Chava, Bharani; Van der Plas, Geert; Verkest, Diederik; Beyne, Eric (2019) -
High-aspect-ratio ruthenium lnes for buried power rail
Gupta, Anshul; Kundu, Shreya; Teugels, Lieve; Boemmels, Juergen; Adelmann, Christoph; Heylen, Nancy; Jamieson, Geraldine; Varela Pedreira, Olalla; Ciofi, Ivan; Chava, Bharani; Wilson, Chris; Tokei, Zsolt (2018) -
Impact of a SADP flow on the design and process for N10/N7 layers
Gillijns, Werner; Sherazi, Yasser; Trivkovic, Darko; Chava, Bharani; Vandewalle, B.; Gerousis, V.; Raghavan, Praveen; Ryckaert, Julien; Mercha, Abdelkarim; Verkest, Diederik; McIntyre, Greg; Ronse, Kurt (2015) -
Low track height standard cell design in iN7 using scaling boosters
Sherazi, Yasser; Jha, Chaitanya; Rodopoulos, Dimitrios; Debacker, Peter; Chava, Bharani; Mattii, Luca; Garcia Bardon, Marie; Schuddinck, Pieter; Raghavan, Praveen; Gerousis, V.; Spessot, Alessio; Verkest, Diederik; Mocuta, Anda; Kim, Ryan Ryoung han; Ryckaert, Julien (2017) -
Power Delivery Network (PDN) modeling for backside-PDN configurations with buried power rails and uTSVs
Hossen, Md Obaidul; Chava, Bharani; Van der Plas, Geert; Beyne, Eric; Bakir, Muhannad (2020) -
SRAM with buried power distribution to improve write margin and performance in advanced technology nodes
Salahuddin, Shairfe Muhammad; Shaik, Khaja Ahmad; Gupta, Anshul; Chava, Bharani; Gupta, Mohit; Weckx, Pieter; Ryckaert, Julien; Spessot, Alessio (2019) -
Standard cell design in N7: EUV vs. immersion
Chava, Bharani; Rio, David; Sherazi, Yasser; Trivkovic, Darko; Gillijns, Werner; Debacker, Peter; Raghavan, Praveen; Elsaid, Ahmad; Dusa, Mircea; Mercha, Abdelkarim; Ryckaert, Julien; Verkest, Diederik (2015) -
TEASE: A systematic analysis framework for early evaluation of FinFET-based advanced technology nodes
Mallik, Arindam; Zuber, Paul; Liu, Tsung-Te; Chava, Bharani; Ballal, Bhavana; Royer Del Barrio, Pablo; Baert, Rogier; Croes, Kris; Ryckaert, Julien; Badaroglu, Mustafa; Mercha, Abdelkarim; Verkest, Diederik (2013)