Browsing by author "Wong, H.-S. Philip"
Now showing items 1-7 of 7
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Density-balancing mask sssignment for via patterning with directed self-assembly
Tung, Maryann C.; Guo, Daifeng; Karageorgos, Ioannis; Wong, Martin D. F.; Wong, H.-S. Philip (2016-10) -
Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits
Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Croes, Kris; Bekaert, Joost; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016-11) -
Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Karageorgos, Ioannis; Ryckaert, Julien; Tung, C. Maryann; Wong, H.-S. Philip; Gronheid, Roel; Bekaert, Joost; Croes, Kris; Karageorgos, Evangelos; Vandenberghe, Geert; Stucchi, Michele; Dehaene, Wim (2016) -
Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)
Tung, C. Maryann; Doise, Jan; Karageorgos, Ioannis; Ryckaert, Julien; Wong, H.-S. Philip (2016) -
Experimental study of sub-DSA resolution assist features (SDRAF)
Yi, Linda; Bekaert, Joost; Gronheid, Roel; Vandenberghe, Geert; Nafus, Kathleen; Wong, H.-S. Philip (2015) -
Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition
Karageorgos, Ioannis; Ryckaert, Julien; Gronheid, Roel; Tung, Maryann C.; Wong, H.-S. Philip; Karageorgos, Evangelos; Bekaert, Joost; Vandenberghe, Geert; Dehaene, Wim (2016-10) -
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
Hills, Gage; Garcia Bardon, Marie; Doornbos, Gerben; Yakimets, Dmitry; Schuddinck, Pieter; Baert, Rogier; Jang, Doyoung; Mattii, Luca; Sherazi, Yasser; Rodopoulos, Dimitrios; Ritzenthaler, Romain; Lee, Chi-Shuen; Thean, Aaron; Radu, Iuliana; Spessot, Alessio; Debacker, Peter; Catthoor, Francky; Raghavan, Praveen; Shulaker, Max M.; Wong, H.-S. Philip; Mitra, Subhasish (2018)