Browsing by author "Chiu, Eddie"
Now showing items 1-5 of 5
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Gate-all-around InGaAs nanowire FETs with peak transconductance of 2200 μS/μm at 50nm Lg using a replacement fin RMG flow
Waldron, Niamh; Sioncke, Sonja; Franco, Jacopo; Nyns, Laura; Vais, Abhitosh; Zhou, Daisy; Lin, Dennis; Boccardi, Guillaume; Sebaai, Farid; Xie, Qi; Givens, M.; Tang, F.; Jiang, X.; Chiu, Eddie; Opdebeeck, Ann; Merckling, Clement; Maes, Jan; van Dorp, Dennis; Teugels, Lieve; Sibaja-Hernandez, Arturo; De Meyer, Kristin; Barla, Kathy; Collaert, Nadine; Thean, Aaron (2015) -
Novel gate stack engineering for high mobility Ge nFETs
Arimura, Hiroaki; Cott, Daire; Loo, Roger; Wostyn, Kurt; Boccardi, Guillaume; Franco, Jacopo; Sioncke, Sonja; Xie, Qi; Tang, Fu; Jiang, Xiaoqiang; Givens, Michael; Chiu, Eddie; Mitard, Jerome; Mocuta, Dan; Collaert, Nadine (2018) -
Observation of plasma-induced damage in bulk germanium p-type FinFET devices and curing in high-pressure anneal
Hiblot, Gaspard; Arimura, Hiroaki; Witters, Liesbeth; Chiu, Eddie; Liu, Yefan; Mitard, Jerome; Horiguchi, Naoto; Collaert, Nadine; Van der Plas, Geert (2019) -
Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability
Arimura, Hiroaki; Witters, Liesbeth; Cott, Daire; Dekkers, Harold; Loo, Roger; Mitard, Jerome; Ragnarsson, Lars-Ake; Wostyn, Kurt; Boccardi, Guillaume; Chiu, Eddie; Subirats, Alexandre; Favia, Paola; Vancoille, Eric; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2017) -
Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal
Arimura, Hiroaki; Cott, Daire; Loo, Roger; Vanherle, Wendy; Xie, Qi; Tang, Fu; Jiang, Xiaoqiang; Franco, Jacopo; Sioncke, Sonja; Ragnarsson, Lars-Ake; Chiu, Eddie; Lu, Xiaowan; Geypen, Jef; Bender, Hugo; Maes, Jan; Givens, Michael; Sibaja-Hernandez, Arturo; Wostyn, Kurt; Boccardi, Guillaume; Mitard, Jerome; Collaert, Nadine; Mocuta, Dan (2016)