Browsing by author "Washington, Lori"
Now showing items 1-6 of 6
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A systematic study of trade-offs in engineering a locally strained pMOSFET
Nouri, Faran; Verheyen, Peter; Washington, Lori; Moroz, Victor; De Wolf, Ingrid; Kawaguchi, S.; Biesemans, Serge; Schreutelkamp, Rob; Kim, Y.; Shen, M.; Xu, X.; Rooyackers, Rita; Jurczak, Gosia; Eneman, Geert; De Meyer, Kristin; Smith, L.; Pramanik, D.; Forstner, H.; Thirupapuliyur, S.; Higashi, G. (2004) -
Exploring the limits of stress-enhanced hole mobility
Smith, Lee; Moroz, Victor; Eneman, Geert; Verheyen, Peter; Nouri, Faran; Washington, Lori; Jurczak, Gosia; Penzin, Oleg; Pramanik, Dipu; De Meyer, Kristin (2005-09) -
Impact of recessed S/D SiGe integration parameters on device performance
Washington, Lori; Nouri, Faran; Verheyen, Peter; Moroz, Victor; Kawaguchi, Marc; Yihwan, Kim; Samoilov, Arkadiii; Jurczak, Gosia (2005) -
Integration of a recessed SiGe Source/Drain into a PMOS transistor
Washington, Lori; Nouri, Faran; Verheyen, Peter; De Wolf, Ingrid; Moroz, Victor; Kawaguchi, Mark; Yihwan, Kim; Samoilov, Arkadii; Jurczak, Gosia (2005) -
Layout impact on the performance of a locally strained PMOSFET
Eneman, Geert; Verheyen, Peter; Rooyackers, Rita; Nouri, Faran; Washington, Lori; Degraeve, Robin; Kaczer, Ben; Moroz, Victor; De Keersgieter, An; Schreutelkamp, Rob; Kawaguchi, M.; Kim, Y.; Samoilov, A.; Smith, L.; Absil, Philippe; De Meyer, Kristin; Jurczak, Gosia; Biesemans, Serge (2005) -
The impact of layout on stress-enhanced transistor performance
Moroz, Victor; Eneman, Geert; Verheyen, Peter; Nouri, Faran; Washington, Lori; Smith, Lee; Jurczak, Gosia; Pramanik, Dipu (2005)