Browsing by author "Nagata, Makoto"
Now showing items 1-8 of 8
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A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
Araga, Yuuki; Miura, Ranto; Nagata, Makoto; Roda Neve, Cesar; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2014) -
A study on substrate noise coupling among TSVs in 3D chip stack
Araga, Yuuki; Nagata, Makoto; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2018) -
Broadband metal-insulator-metal capacitors on silicon interposer for low impedance power distribution network
Ueda, Nao; Roda Neve, Cesar; Detalle, Mikael; Beyne, Eric; Van der Plas, Geert; Nagata, Makoto (2015) -
CDM protection of a 3D TSV memory IC with a 100 GB/s Wide I/O data bus
Nagata, Makoto; Takaya, Satoshi; Ikeda, Hiroaki; Linten, Dimitri; Scholz, Mirko; Chen, Shih-Hung; Hasegawa, Keiichi; Shintani, Taizo; Sawada, Masanori (2014-09) -
In-tier diagnosis of power domains in 3D TSV ICs
Araga, Yuuki; Nagata, Makoto; Van der Plas, Geert; Kim, Jaemin; Minas, Nikolaos; Marchal, Pol; Travaly, Youssef; Libois, Michael; La Manna, Antonio; Zhang, Wenqi; Beyne, Eric (2012) -
Measurements and analysis of substrate noise coupling in TSV based 3D integrated circuits
Araga, Yuuki; Nagata, Makoto; Van der Plas, Geert; Marchal, Pol; Libois, Michael; La Manna, Antonio; Zhang, Wenqi; Beyer, Gerald; Beyne, Eric (2014-06) -
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements
Monta, Kazuki; Katselas, Leonidas; Fodor, Ferenc; Miki, Takuji; Hatzopoulos, Alkis; Nagata, Makoto; Marinissen, Erik Jan (2022) -
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring
Monta, Kazuki; Kataselas, Leonidas; Fodor, Ferenc; Hatzopoulos, Alkis; Nagata, Makoto; Marinissen, Erik Jan (2021)